USB 3.0 PHY IP Core
The USB 3.0 PHY is a complete, mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into USB 3.0 SuperSpeed ...
Source: design-reuse.com
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USB 3.0 PCIe 2.0 SATA 3.0 Combo PHY IP, Silicon Proven in SAMSUNG 8LPP
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE interface spec, ...
Source: design-reuse.com
USB 3.0 SATA 3.0 PCIe 2.0 XAUI MultiPHY IP Core
The Innosilicon Multi-SERDES PHY is a highly configurable design that supports SATA3, PCIe2, USB3.0 and XAUI with full compliance. It is available in ...
Source: design-reuse.com