Meet UVVM: The World's #1 VHDL Verification Methodology – EEJournal
I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that the last time I turned my attention to this arena, people were saying that the design and verification phases of a complex device consumed…
Source: eejournal.com