Riviera-PRO™: OSVVM 2020.08 inclusion, enhanced language support, and new debugging features aim to boost productivity
Riviera-PRO™: OSVVM 2020.08 inclusion, enhanced language support, and new debugging features aim to boost productivity Henderson, NV – December 8, 2020 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated Riviera-PRO™ to include the 2020.08 revision of the open-source VHDL verification methodology (OSVVM). This gives users of Aldec’s popular simulation platform access to OSVVM’s new requirements tracking, updated scripting, AXI4 full verification components, and model independent transactions. The ...
Source: eejournal.com