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Silexica’s New SLX FPGA 2020.4 Ushers in a New Level of Usability San Jose, CA – January 11, 2021 – Silexica (silexica.com) has announced the release of SLX FPGA 2020.4 to expand the adoption of high-level synthesis (HLS) for FPGA designs. This release includes a new interactive, task-based flow that walks HLS users through the design flow from start to finish. The task-based flow recommends next steps and possible analysis results relevant to the user at each step in the flow. In addition, SLX FPGA 2020.4 incorporates optimizations to the profiling capability that allow designers to un...

Facilitating Abstract Hardware Design by Kevin Morris The history of digital hardware design is one of managing ever-increasing complexity by raising the level of design abstraction. When our digital circuits had four inputs, it was completely reasonable to do logic minimization with a Karnaugh map. When sequential logic was involved, a state diagram was a nice way to work things out, and we could generally draw a single page schematic with a dozen or so logic gates describing our implementation. As the number of logic gates soared, though, those schematics became hundreds...