Sondrel cuts verification time with new, enhanced, work flow modelling tools – CIE
December 11, 2020 529 Views The problem with assembling IP blocks onto a chip is that it can be hard to work out how they will interact with one another and the memory. Whilst the IP blocks will have been pre-verified individually by the vendors, the key questions are how well they work together and, more importantly, how to optimise this. Sondrel has developed new enhanced workflow modelling tools for this purpose that reduce time to market, cut customer costs and optimise architectural design. “Synopsys ® has a modelling tool called Platform Architect™ Ultra,” explained Paul Martin...
Source: cieonline.co.uk