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MIPI D-PHY 4 Lane CSI2-TX 1.2G in TowerJazz 110nm The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized for camera interface applications (CSI-2). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control. View see the entire get in contact with Block Diagram of the MIPI D-PHY 4 Lane CSI2-TX 1.2G in To...

AES (ECB-CBC-CFB-CTR), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumption compared to running the same algorithms in software. The Crypto Accelerator Hardware Cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution, offering various levels of cryptographic acceleration performance. They are easy to integrate into various So...

Audio I2S-TDM Transceiver The IObundle I 2 S/TDM Transceiver core is a configurable audio interface core with transmission and receiving capabilities. It supports master/slave, internal DMA, multi-channel and several sample sizes and frame formats. The IP is currently supported for use in ASICs and FPGAs. View see the entire

MIPI C-PHY/D-PHY Combo IP CSI-2 TX+, 3.5Gsps/2.5Gbps The MXL-CDPHY-2p5G-CSI2-TX+-40LP is a high-frequency, low-power, low-cost, source synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1 and C-PHY v1.2. The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in-system testing while minimizing area and leakage power. View see the entire get in contac...

DMA Back-End Core The Northwest Logic DMA Back-End Core from Rambus provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. Key features which contribute to this flexibility include: • Works with Northwest Logic soft Expresso Cores and FPGA hard cores • Can be configured with multiple independent DMA Engines which each have their own user interface • Supports Packet/Block and Addressed/Non-addressed transfers • Supports host –based and local descriptors...