CC-100IP-RF Analog and RF Sensitivity Enhancement IP
The CC-100IP-RF is a RF and Analog Frontend Sensitivity Enhancement IP Block that embeds a Hyper-Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and Energy Harvesting capabilities. The IP accomplishes Signal Sensitivity Enhancment by improving the PSRR of sensitive RF and Analog front end receivers. CC-100IP-RF Hyper-Bypass Capacitor creates an adjustable Impedance controlled point in IC power grids aiding in maximum on chip supply line filtering, Impedance matching for Power Grid flat frequency response, showing an up to a 600X improvement in effective and reservoir capacitance. The IP features a circuit noise activated dynamic input current controlled reservoir capacitance, and can function as a “stand-alone” on Chip DCAP, or work in parallel with existing DCAP structures. Due to the embedded IP negative feedback, the CC-100 features a 25% reduction in Hyper-Capacitor effective series inductance (ESL). The IP operates by feeding back a portion (nominally 20%) of the bypass current flowing through IP input base capacitors, feeding back current onto the chip power grid, preventing bypass Capacitor Deep discharge, thus reducing overall chip dynamic power draw. These effects substantially reduce RF Emissions and increase RF sensitivity for RF and Analog Frontends, making them more sensitive to input signaling, making systems less vulnerable to cyber hacking, and more secure The IP draws no current for operation, thus maximizing block efficiency.