May 27, 2021
Synopsys DesignWare PVT Subsystem Drives Performance, Power and Silicon Lifecycle Management on TSMC’s N3 Process Technology
Real-Time Chip Insights Provide Optimized Device Utilization Throughout the Silicon Lifecycle for Leading Market Applications
MOUNTAIN VIEW, Calif., May 27, 2021 /PRNewswire/ —
Highlights for this Announcement:
DesignWare PVT monitoring and sensing subsystem IP supports cutting-edge technologies targeting AI, data center, HPC, consumer and 5G markets
Innovative, modular architecture offers new sensor technologies for advanced node devices
Designers benefit from a complete PVT subsystem providing real-time insights within the chip
® process, voltage and temperature (PVT) monitoring and sensing subsystem IP on TSMC’s industry-leading N3 process technology. The PVT monitoring and sensing subsystem IP has been added to the TSMC9000 Program, TSMC library and IP quality management program, offering customers a highly competitive performance advantage for a wide variety of target market applications including artificial intelligence (AI), data center, high-performance computing (HPC), consumer and 5G. SoC designers targeting TSMC’s most advanced process can utilize the deeply embedded PVT monitoring and sensing subsystem technology to assess key chip parameters during production as well as for measurement and analysis of real-time dynamic conditions during every stage of the device life cycle.