Codasip University Program News Today

Structured sparsity involves a predefined pattern of zero values in the matrix, unlike unstructured sparsity where zeros can occur anywhere.

Codasip, the leader in processor design automation and RISC-V processor IP, today announced the establishment of Codasip Labs as an innovation hub within the company.

Codasip has announced that it is collaborating with Intel to enable undergraduate and graduate level courses to benefit from faster, simplified architectural exploration combining Codasip RISC-V IP cores, the Codasip Studio development environment, and Intel's FPGA platforms.

Codasip, the leader in processor design automation and RISC-V processor IP, today announced it is collaborating with Intel® to enable undergraduate and graduate level courses to benefit from faster, simplified architectural exploration combining Codasip RISC-V IP cores, the Codasip Studio development environment, and Intels FPGA platforms.

With closed processor Instruction Set Architectures (ISA) with limited access to processor Intellectual Property (Arm and x86), university professors ...

Keith Graham appointed Head of University Program

Keith Graham appointed Head of University Program Munich, 10 March 2022 – Codasip, the leader in processor design automation, has launched a University Program to help the next generation of processor engineers to Design for Differentiation and to solve tomorrow’s technological challenges...