Codasip Studio News Today

Structured sparsity involves a predefined pattern of zero values in the matrix, unlike unstructured sparsity where zeros can occur anywhere.

The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than ...

Codasip, the  RISC-V Custom Compute specialist, has announced the first commercial implementation of CHERI (Capability Hardware Enhanced RISC Instructions

Codasip, the RISC-V custom compute specialist, has brought out a configurable family of RISC-V baseline processors. The 700 family includes application

Codasip has announced the launch of a highly configurable family of RISC-V baseline processors.

The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage ...

Codasip, RISC-V Custom Compute specialist, now offers Siemens EDA’s Tessent Enhanced Trace Encoder product with its customisable RISC-V cores, allowing

Codasip, a leader in RISC-V Custom Compute, is now offering the Tessent Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line at Siemens EDA with its customisable RISC-V cores.

Codasip® now offers the Tessent™ Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line at Siemens EDA with its customizable RISC-V cores. Through the joint solution, developers can efficiently trace and debug issues between silicon and software, and accurately understand real-time behaviors of even the most complex customized designs based on Codasip RISC-V processors™.

Codasip Labs is all about innovation, and specifically the commercialization of that innovation. Naturally, with the rise of Artificial Intelligence (AI) ...