Last Level Cache News Today

My friend Jim Handy (The Memory Guy) recently published a blog about Compute Express Link (CXL) and two conundrums he perceives about the technology. CXL is a relatively new cache-coherent memory protocol based on open standards that’s designed to make large memory pools available to multiple processors in large computer systems and data centers. CXL’s…

CodaCache is a configurable, standalone, non-coherent cache IP that delivers unique business value through its advanced last-level cache (LLC) architecture, ...

New information regarding the Intel LGA 1851 platform which will feature support for the next-gen Arrow Lake Desktop CPUs has been revealed.

Unlike Microsoft's Windows 11, next-gen Linux will not only support older AMD Ryzen processors, but they could even get some decent performance boosts too. This is suggested by a recent patch.

Intel Patches within Linux have confirmed that 14th Gen Meteor Lake CPUs will make use of L4 cache that should assist the Arc Xe-LPG GPUs.

- Introduction of the world's highest performance* vector supercomputer at Tohoku University -TOKYO, Oct 7, 2022 - (JCN Newswire) - NEC Corporation (TSE: 6701) will launch the new "SX-Aurora TSUBASA C401-8"

Business Scoop provides news and views on Business and Markets from New Zealand

GUC announces GLink-3D Die-on-Die interface IP Global Unichip (GUC), an ASIC developer, has announced GLink-3D die-on-die interface IP using TSMCs N5 and N6 processes and 3DFabric advanced packaging technology for AI, HPC, and networking applications. With AI, HPC and networking memory demand growing there is a need for SRAM/Logic disintegration allowing the implementation of separate SRAM and Logic at the most efficient process nodes. Layers of CPU and SRAM (Last Leve...

05/24/2021 | Press release | Distributed by Public on 05/24/2021 00:14 GUC Announces GLink-3D Die-on-Die Interface IP using TSMC N5 and N6 Process for 3DFabric™ Advanced Packaging Technology Hsinchu, Taiwan - May 24, 2021 - Global Unichip Corp. (GUC), the Advanced ASIC Leader, announces GLink-3D die-on-die interface IP using TSMCs N5 and N6 processes and 3DFabric™advanced packaging technology for AI, HPC, and Networking applications. AI/HPC/Networking memory demand is growing quickly ...

Apr 5, 2021 12:04 EDT AMD has published a new patent in which the company talks about an active chiplet serving as a bridge between multiple GPU dies, possibly based on its next-generation RDNA 3 architecture for GPUs and APUs. AMD Active Bridge Chiplet Patent Might Give Us A Glimpse of The Next-Gen RDNA 3 Graphics Architecture Based GPUs and APUs The patent starts off by stating the elephant in the room and thats conventional monolithic GPU designs. We all know how well chiplets worked ou...