32-bit SPARC V8 processor IP Core
The LEON3 processor is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 acrhitecture. The model is highly configurable, and ...
Source: design-reuse.com
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RSA-ECC Public Key Accelerator Engine, 50K ops/sec
Rambus DPA Resistant PKEv2, PKEv3, PKEv4 Cryptographic Accelerator Cores prevent against the leakage of secret cryptographic key material through attacks ...
Accelerator Cores Cipher Block Chaining Authenticated Encryption Galois Counter Public Key Sa Ecc Public Key Accelerator Engine
Source: design-reuse.com
LPDDR4 multiPHY V2 in Samsung (14nm, 10nm)
LPDDR4 multiPHY: Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps - Maximum data rate is process technology dependent - Compatible with JEDEC ...
Source: design-reuse.com
32-Bit SPARC V8 Processor IP Core
The LEON5 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and suitable ...
Source: design-reuse.com
32-kHz Bandwidth Reconfigurable Delta-Sigma ADC providing up to 13 ENOB
A solution including an input buffer with programmable gain, followed by a Delta Sigma Modulator (DSM) and a Decimation filter is provided. Additionally, ...
Delta Sigma Modulator Delta Sigma Adc Pad Converter 2 Khz Bandwidth Reconfigurable Delta Sigma Adc Providing Up To 13 Enob 2 Khz Bandwidth Reconfigurable Delta Sigma Adc P Core
Source: design-reuse.com
SpaceWire Routing Switch IP Core
The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard. The core is highly configurable, flexible ...
Remote Memory Access Protocol Spacewire Plug And Play Ecsse St 50 12c Pacewire Routing Switch Rspwrouter P Core
Source: design-reuse.com
MIPI C-PHY v2.0 / D-PHY v2.1 PHY IP on TSMC N5
Synopsys’ integrated DesignWare C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, for mobile, automotive, ...
Mipic Phy Mipid Phy Tsmc N5 Tsmc 5nm Esignwarec Phy V2 0d 1 Ip On Tsmc N5 Wc Mipi Cd 20 21 Rx 3t4l Tsmc5ff12ns
Source: design-reuse.com
DVB-S2X LDPC Decoder ASIC or FPGA
The DVB-S2X LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design for ...
Digital Video Broadcasting Dvb S2x Vb S2x Ldpc Decoder Asic Or Fpga Vb S2x Ldpc Decoder Asic Or Fpga Global Ip Core P Core Ilicon Ip
Source: design-reuse.com
TSMC CLN7FF 7nm General Purpose PLL - 400MHz-2000MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider ...
Source: design-reuse.com
AXI Interface Core
Rambus’s AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). The core accepts write and read ...
Xtensible Interface Bus Master Memory Controller Bus Functional Read Modify Write Core Xi Interface Core
Source: design-reuse.com