Page 113 - P Core News Today

Rambus PCIe 2.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 ...

The Alphawave CDPCS IP core is a cutting-edge solution to the 800/400/200G Ethernet application. It supports the Physical Coding Sublayer (PCS) for 64B/66B ...

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol ...

The eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and I/O technologies: SD, SDIO and eMMC memory formats. This IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.

OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OMC is the ORBITTM DDR Memory Controller, ...

Rambus Hardware Root of Trust RT-130 is a state-machine-based hardware security core offering security by design. It protects against a wide range of ...

Body biasing is a disruptive 22FDX® feature enabling onthe-fly adaption of transistor threshold voltages. Racyics® Adaptive Body Biasing (ABX) technology ...

The Rambus Mem Test Analyzer Core from Rambus is used to capture the results from Rambus Memory Test Core. The Mem Test Analyzer Core can be used in ...

The Alphawave FlexE SHIM IP core (FlexE SHIM) is cutting edge solution to the Ethernet application. It integrates seamlessly with Alphawave s MC MAC Core ...

The OTU0/ODU0 Digital Wrapper IP Core offers 1.25G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation. ...