Page 115 - P Core News Today

Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is ...

Chips&Media’s Camera ISP IP – METIS (hereafter will be referred as METIS ISP) is Image Signal Processing (ISP) IP developed to be used automotive ...

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

Mindtree IEEE 802.15.4 MAC and PHY semiconductor Intellectual Property (IP) is based on IEEE 802.15.4 specification. This standard defines the Physical ...

The Trilinear Technologies Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K. ...

The Protocol-IP-338 (EIP-338) is a scalable, high-performance, multi-stream cryptographic engine that offers XTS and GCM modes of operation for the AES ...

Silicon proven in TSMC40nm ULP, this GNSS Ultra-low power RF Receiver IP supports all existing satellite-based navigation systems including GPS (US), ...

Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retimer. ...

VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirements. The processor also ...

Rambus Hardware Root of Trust RT-630 is a fully-programmable hardware security core offering security by design. It protects against a wide range of attacks ...