Bluetooth Low Energy 5.2 Wireless Baseband Processor IP
The LP-BLE is a power and area-optimized Bluetooth Low Energy Controller designed to bring secure wireless connectivity to various ultra-low-power and ...
Source: design-reuse.com
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MIPI D-PHY CSI-2 TX 2.5Gbps/lane
The MXL-D-PHY-CSI2-TX-T-65LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...
Source: design-reuse.com
TLS 1.3 Client IP Core IP Core
XIP7131C is a compact 1 Intellectual Property (IP) core for TLS 1.3 client-side functionality. Transport Layer Security (TLS) is a cryptographic protocol, ...
Player Security True Random Number Generator Transport Layer Security Cryptographic Protocol Ls 1 3 Client Ip Core P Core
Source: design-reuse.com
PUF-based True Random Number Generator IP Core
A random number generator (RNG) is an essential function for security solutions. The security strength of many systems and applications depends on a high ...
National Institute Of Standards National Institute Puf True Random Number Generator Uf Based True Random Number Generator P Core Ilicon Ip
Source: design-reuse.com
MIPI CSI-2 Controller Core
The Rambus CSI-2 Controller Core V2 is the second generation CSI-2 controller core. It is further optimized for high performance, low power and small ...
Byte Packing Low Level Protocol Lane Management Local Interface Vsync Video Interface Contact Rambus
Source: design-reuse.com
SONET/SDH: OC48/STM-16 Framer IP Core
The SONET/SDH Concatenated/Non-concatenated STS-48/STM-16 core implements the STS-48 and STM-16 layer function of Telcordia GR-253-CORE/ITU-T G.707, supporting ...
Source Frame Sink Framer Payload Extractor Sonet Sdh Oc48 Stm 16 Framer Sonet Sdh Oc48 Stm 16 Framer Megacore Sonet Sdh Oc48 Stm 16 Framer
Source: design-reuse.com
HBM3 PHY
The Rambus High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. The memory ...
Source: design-reuse.com
QSGMII/SGMII/1000BASE-X and MAC IP Core
The fully integrated 5G QSGMII, 2.5G/1.25G SGMII and 1000BASE-X Physical Coding Sublayer (PCS-X) and Media Access Controller (MAC) core for Ethernet applications ...
Media Access Controller Tri Mode Core 000base X Sgmii 1000basex And Mac Megacore Qsgmii Sgmii 1000basex And Mac P Core
Source: design-reuse.com
10G/25GBASE-R PCS+KR4 FEC IP Core
The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant with ...
Physical Coding Sublayer Media Access Controller 10g 25gbaser Pcs Kr4 Fec Pri 8 9 And 10 Pcs Mode 0g 25gbaser Pcs Kr4 Fec Ip Core
Source: design-reuse.com
IEEE1588 & IEEE802.1AS PTP Ordinary Clock (OC) core
The PTP Ordinary Clock (OC) from NetTimeLogic is an extension to a single port of NetTimeLogics PTP Transparent Clock (TC). It adds the Sync and Announce ...
Eee802 1as Ordinary Clock Tp Oc Precision Time Protocol Eee1588 Amp Ieee802 1as Ptp Ordinary Clock Oc Core Tl Ptp Oc
Source: design-reuse.com