Page 128 - P Core News Today

The DesignWare® MIPI CSI-2 Host Controller IP is a fully verified and configurable controller IP that implements all protocol functions defined in the ...

The Silicon Creations wide-range 250Mbps to 8.1Gbps 2-lane Deserializer and Serializer macro includes all high-speed analog functions for four lanes of ...

The Universal Flash Storage 2.0 (UFS 2.0) is a simple but high performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.

The world we know today is becoming more and more connected, with increasingly sophisticated, always connected, devices. People have come to rely on high-speed ...

"The CetraC Switch IP core is the ideal solution to interconnect any Ethernet, TSN and ARINC 664 Part 7 (AFDX) equipment for safety critical application. ...

Chips&Media’s Camera ISP IP – LEDA is the Imaging Signal Processing (ISP) targeted to be used in low light environment for surveillance camera, automotive ...

The Rambus High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. The memory ...

The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The ...

The vDMA-AXI IP Core implements a highly efficient, configurable DMA engine specifically engineered for Artificial Intelligence (AI) optimized SoCs and ...

The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It allows ...