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January 8, 2022
The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY ...
January 7, 2022
The MXL-DPHY-CSI2-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. The ...
January 7, 2022
The Synopsys DesignWare® USB 3.0 femtoPHY and DesignWare® USB-C 3.0 femtoPHY provide designers with a complete physical (PHY) layer IP solution for ...
January 6, 2022
The Protocol-IP-196 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, DTLS, 3GPP and MACsec up to 10 Gbps in multi-core ...
January 6, 2022
The EIP-96 is an Inline Cryptographic Accelerator designed to accelerate and offload the very CPU intensive IPsec, MACsec, SRTP, SSL, TLS and DTLS protocol ...
January 6, 2022
The PowerVR Series9XM family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter ...
January 6, 2022
PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance ...
January 6, 2022
The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus ...
January 5, 2022
The integrated ultra-low power receiver technology RFicient® was developed for ISM frequency bands and built in standard CMOS technology. The receiver ...
January 5, 2022
The bidirectional MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. The MIPI D-PHY analog IP is available in foundry processes spanning 28nm to 180nm.