Page 132 - P Core News Today

The Dual 12b 20 to 200MS/s 1.2V ADC achieves 11 ENOB conversion linearity. It is built around a fully differential proprietary enhanced pipeline converter and a digital error correction circuitry.

The JESD204B RX Physical Coding Sublayer IP Core enables the reception of data via a configurable number of lanes from a Deserializer interface, while guaranteeing data alignment and frame synchronization.

SureCore’s EverOn™ Single Port Synchronous Ultra Low Voltage SRAM IP combines high-density foundry bitcells with sureCore’s low-voltage and low-power ...

FlexWay is for design teams who use multilayer AHB but are looking for a scalable solution to address their future needs and automation of interconnect ...

Arasans Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host processing ...

The demand for advanced multimedia features is pushing device manufacturers to integrate more advanced peripherals such as multi-megapixel cameras and ...

Vivante Image Signal Processor is an industry leading full camera ISP IP, featuring sophisticated pixel processing for wearable device, smart home, video ...

DesignWare® ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on devices to ...

Hillcrest Labs, a CEVA company, is a leading global supplier of software, components and intellectual property to enable the intelligent use of sensors ...

Rambus’s AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). The core accepts write and read ...