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December 18, 2021
The DPA Resistant AES solution implements the AES algorithm with built-in robust, flexible side-channel resistance validated and optimized for different ...
December 18, 2021
NSCores PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the hot carrier effect to trap ...
December 18, 2021
The icyflex-V 32-bit processor core is based on the RV32IMC open-instruction set architecture (ISA) defined by the RISC-V foundation and, as such, is ...
December 17, 2021
The eSi-1650 16-bit CPU with instruction cache is targeted specifically for low-power applications, where typically an 8-bit CPU may have previously been ...
December 17, 2021
Tamba Networks offers a highly configurable, extremely low latency, low gate count, Ethernet MAC & PCS soft core. The core is IEEE compliant. The ...
December 17, 2021
TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compression ...
December 17, 2021
TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compression ...
December 17, 2021
Safe Connect Systems (SCS) IP Cores allow to design full deterministic TSN critical applications with a full range of undisputed assets: โข TSN stack ...
December 16, 2021
Bluetooth Mesh specifications are defined by the Bluetooth Special Interest Group to enable an interoperable mesh networking solution on Bluetooth low ...
December 16, 2021
Body biasing is a disruptive 22FDXยฎ feature which enables the adaption of transistor threshold voltages after production during device operation. Racyicsยฎ ...