SM4 Crypto Engine IP Core
The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of China. It is compliant ...
Source: design-reuse.com
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MIPI D-PHY, CSI-2 TX+ for TSMC40ULP
The MXL-D-PHY-CSI-TX+-T-40ULP is a high-frequency, low-power, low-cost, source synchronous,physical Layer supporting the MIPI Alliance Specification for ...
Source: design-reuse.com
Hardware and software platform for contextually aware IoT devices
SenslinQ is a unique hardware and software platform for linking various sensor processing elements and present them to the Host processor OS or user application. ...
Sensor Fusion Linux Based Hardware Abstraction Layer Voice Processing Nhanced Speech Intelligibility Noise Reduction Speech Recognition
Source: design-reuse.com
Rambus HBM2/2E Memory PHY IP Core
Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor and power-efficient ...
Source: design-reuse.com
PUFkeyst - PUF-based Key Storage IP Core
Most widely used embedded key storage methods are based on One-Time Programmable (OTP) memory such as fuses or anti-fuses, or on Non-Volatile Memory (NVM) ...
One Time Programmable Non Volatile Memory Puf Key Storage Ufkeyst Puf Based Key Storage P Core Ilicon Ip
Source: design-reuse.com
Cache Coherent Interconnect IP Core
For scalable and area-efficient heterogeneous cache coherent systems. Arteris Ncore™ Cache Coherent Interconnect IP implements the same philosophy ...
Arteris Ncore Cache Coherent Interconnect Noc Interconnect Nterface Scheduler Cache Coherent Interconnect P Core
Source: design-reuse.com
High Performance 64-bit RISC-V Multi-Core Application Processor
The U7 Series features SiFive’s highest-performance RISC-V Linux-capable application processor. The U7 core has a superscalar 8-stage pipeline with ...
Edge Compute Big Data Analytics Igh Performance 64 Bit Riscv Multi Core Application Processor 17 Series P Core Ilicon Ip
Source: design-reuse.com
MIPI C-PHY/D-PHY Combo Receiver IP Core
The MXL-CPHY-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave supporting camera ...
Source: design-reuse.com
High performance Linux capable vector processor
The SiFive Intelligence VIU75 Standard Core is a single-core instantiation of our RISC-V application processor with vector extensions and is capable of ...
Sifive Intelligence Risc V Igh Performance Linux Capable Vector Processor P Core Ilicon Ip Emiconductor Ip
Source: design-reuse.com
MIPI D-PHY TSMC 40LP IP Core
The MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. It is a universal PHY that can be configured as a transmitter, receiver or transceiver. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions.
Source: design-reuse.com