Page 158 - P Core News Today

The PowerVR Series9XE family features include: an advanced scalable compute cluster architecture; high efficiency compression technology including parameter ...

The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, ...

The MIPI D-PHY Receiver is a high-frequency low-power, low-cost, sourcesynchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display interface applications (DSI).

The INNOSILICON Mixed-Signal LPDDR4/3/2 DDR4/3/2 Combo PHYs with industry standard DFI V2.1 interface provide the most advanced physical interface solutions ...

Our patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy ...

The Serial Flash Controller Design IP offers a rich set of features to facilitate easy access to Serial Flash devices. The CPU can boot directly from the Serial Flash through the memory emulation interface.

The BLE5ZSUBGS40LP RF IP is designed for SMIC 40nm LP Process. It is a cost-effective low power dual-band communication sub-system. It integrates TX/RX ...

The MXL-DPHY-CSI2-TX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for ...

Analog Bits PVT Sensor is a highly integrated macro for monitoring process, voltage, and temperature variation on-chip, allowing very high precision even ...

Synopsys DesignWare® DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR4, DDR3, LPDDR2, ...