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The EIP-12 SM4 Engine implements the SM4 cipher block algorithm. The accelerator includes I/O registers, encryption and decryption cores. Designed for ...

High performance 32-bit RISC-V Processor The E3 Series is highly-integrated and feature-rich. It includes the E31 Core, which is the most widely deployed RISC-V core in the world. E3 embedded cores have a 5-6 stage pipeline, offering a great balance between performance and efficiency. View see the entire get in contact with © 2021 Design And Reuse All Rights Reserved. No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express writt...

Automotive MIPI A-PHY Source IP - 1-Lane The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS and autonomous drive subsystems. It supports applications that require long reach (up to 15 meters), error-free links, and high EMI immunity requirement. PHY IP supports the SOURCE function of MIPI A-PHY Gear-2 stated in standard specification. It supports data rate up to 4Gbps with integrated mixed s...

FIPS 140-3 compliant True Random Number Generator (TRNG) The EIP-76 TRNG is an advanced hardware based, technology independent True Random Number Generator. Security is now a basic requirement for all devices. To support that requirement, semiconductor designers must build strong cryptographic capabilities into their chips, capabilities that begin with a True Random Number Generator (TRNG). A TRNG is used for the generation of keys, initialization vectors, cookies, and nonces; it is an esse...

FPGA Evaluation Platforms for RISC-V Processor Cores This FPGA platform aims to simplify the evaluation of a Codasip low-power (L family) or high-performance (H family) embedded cores. The platform is available to companies with an evaluation agreement. The subsystem is based on AHB and provides a variety of commonly-used peripherals which enable the rapid testing and assessing of a core on an Xilinx-based Digilent Nexys A7 FPGA board. View FPGA Evaluation Platform for Codasip Applicat...

Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is ...

The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible with MIPI Specification for D-PHY v1.2. The IP is configured as a MIPI master optimized for CSI-2SM (Camera Serial Interface) applications. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for high-Speed data traffic while low powe...

USB-C 3.2/DisplayPort PHY IP for Samsung 4LPE The DesignWare USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or Dual-Role Device) with HDCP 2.2 content protection, verification IP, and IP subsystems. These elements accelerate development of advanced chip designs delivering video, data and power over a single Type-C connector. Synopsys DesignWare USB 3.2 solution is certified by the USB-IF and DesignWare 1...

AI accelerator - 2.25K, 4.5K, or 9K INT8 MACs Origin E2 is designed for low power applications such as mobile phones. It uses on-chip memory only. By eliminating the need for DRAM access, it saves system power while increasing performance, reducing latency, and cutting BOM costs. Its highly efficient engine uses less than 1W. Origin E2 is tunable for specific workloads to provide an optimal performance profile for unique application requirements. View see the entire get in contact wit...

Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol. sFPDP is ideal for use in ...