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32-bit Embedded RISC-V Functional Safety Processor 32-bit Embedded RISC-V Functional Safety Processor The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing the RISC-V Instruction Set Architecture (ISA). The Harvard architecture EMSA5 processor implements a single-issue, in-order, 5-stage execution pipeline, supporting the RISC-V 32-bit base intege...

DesignWare 112G Ethernet PHY IP for TSMC N7 Process The DesignWare 112G Ethernet PHY IP enables true long reach channels for up to 800G hyperscale data center SoCs requiring high bandwidth and low latency. Using leading-edge design, analysis, simulation, and measurement techniques, the 112G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3ck and OIF standards electrical specifications. The PHY is small in area, high in performance, and su...

Controller IP for PCIe 6.0, Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with Native User Interface XpressRICH™ Controller IP for PCIe® 6.0 is a configurable and scalable PCIe controller Soft IP designed for ASIC implementation. The XpressRICH Controller IP for PCIe 6.0 supports the PCIe® 6.0 specification, including 64GT/s data rates, PAM4, FLIT mode, and L0p power state, as well as version 6.x of the PHY Interface for PCI Express (PIPE) specification. Backward...

Chips&Media’s WAVE515 is one of the most advanced hardware video decoder IP core which supports the next generation HEVC(High-Efficiency Video Coding) ...

Rambus Cryptographic Accelerator Core SHA-2-Compact Rambus Crypto Accelerator SHA-2-Compact Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumption compared to running the same algorithms in software. The Crypto Accelerator Hardware Cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution, offering various levels of cryptographic acceler...

The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 512 ...

The S3DA160M12BT22ULL employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which ...

The MXL-CD-PHY-DSIRX-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

The Synopsys DesignWare Embedded Security Modules (ESMs) for HighBandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide ...

PCIE 5.0 PHY in Samsung 10/8LPP, SMIC 14SFE/SF+, and TSMC 12FFC Wednesday May. 05, 2021 PCIE 5.0 PHY in Samsung 10/8LPP, SMIC 14SFE/SF+, and TSMC 12FFC Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane.32G Serdes including PCIe 5/4/3- Compatible with next generation PCIe standard protocol.Supporting various serial interface protocols within 32Gbps.(Pcle4.0/pcle5.0/Rapid IO/XAUI/SATA/fiber channel/10G Ethernet etc.) View ...