Page 168 - P Core News Today

The ntOFDM_HS_BBP IP implements the physical layer transmission and reception processing engines of a custom subset of the 802.16-2012 standard. The ntOFDM_HS_BBP ...

The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data established by the U.S National Institute of Standards ...

Universal fully-integrated fault attack sensor In cryptography, an attack can be performed by injecting one or several faults into a device thus disrupting ...

DPA Resistant Cryptographic Accelerator Core PKEv2 Rambus DPA Resistant PKEv2, PKEv3, PKEv4 Cryptographic Accelerator Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. The DPA Resistant Hardware cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions across a wide array of devices. These high-performance cores...

1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI) eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ultra-high speed SerDes IP is adopted by global Tier1network/storage/5G OEMs and major semiconductor companies. Our solution is also applicable to fastgrowing Al applications. eTopus was among the first startup company to provide ADC/DSP-based 56Gbps SerDes IP for...

Configurable PCI Express 1.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect XpressRICH-AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH-AXI Controller IP for PCIe 1.1 is compliant with the PCI Express 1.1 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification. The IP can be configu...

Interlaken is a royalty-free interconnect protocol that was developed by Cisco Systems and Cortina Systems in 2006. The full Interlaken protocol (described ...

The IPLDOGF22 is a low drop-out regulator (LDO) that produces a low-noise DC voltage as regulated power supply for a target block. It is based on a ...

MIPI UFS v3.1 Host Controller IP, Compatible with M-PHY and Unipro Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification. The UFS standard is a high performance, low power serial interface that efficiently moves data between a host processor and mass storage devices. When our UFS Controller IP is combined with in-house developed UniPro Controller IP and M-PHY IP, designers can easily integrate PHY and the controller with low risk and accel...

This block is an oscillator circuit used to provide an accurate 20 MHz clock signal. It operates from a regulated 1.5 V supply voltage with a typical ...