Page 166 - P Core News Today

CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control data between wireless ...

An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS ...

Our LDPC encoding and decoding IP for the 3GPP New Radio uplink and downlink data channel includes the entire processing chain, to provide quick and easy ...

Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. ...

The MXL-D-PHY-DSITX-T-55ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

The Rambus High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. The memory ...

Arasan Chip Systems Quad SPI (QSPI) master core is easy to use, simple to work with, quick to operate, and reliable under all conditions. It supports ...

SM3 is a hash algorithm initially published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA in 2010, then as a China industry ...

<b>Off-loading heavy calculations from microcontrollers</b> The DR1000C is a parallel processor IP that is ideal for offloading high-load arithmetic ...

The HMAC SHA AES Accelerator is a low-power low-gate count crypto core with DMA capability and local key storage.