Page 167 - P Core News Today

Analog Bits PVT Sensor is a highly integrated macro for monitoring process, voltage, and temperature variation on-chip, allowing very high precision even ...

Our Turbo decoding IP core for the 3GPP LTE uplink and downlink uses a novel architecture, which facilitates much higher degrees of parallel processing ...

RSA is a public-key cryptosystem (the encryption key is public when the decryption key is private) widely used for secure data transmission. This IP ...

The PVT Sensor is an IP block which monitors chip Process, Voltage, and Temperature (PVT) providing a high accuracy measurement result. The sensor consumes ...

GDDR6 PHY - TSMC12FFc With the advancement of artificial intelligence (AI), deep neural networks (DNN), ADAS, and high-performance computing (HPC), there is an ever-increasing demand for higher memory bandwidth. Along with the large amount of data generated by these applications, the memory sub-system plays a crucial role in the overall performance. TSS GDDR6 PHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedanc...

IMG B-Series takes all of the advances of IMG A-Series, the fastest GPU IP ever created, and offers new configurations with even higher levels of performance. ...

Ethernet TSN MAC 10G/25G Comcores TSN MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption and 802.3br Interspersing Express Traffic. This enables the use of the MAC in high-speed time-critical applications. The MAC-core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum. The core is fu...

LEE Flash G1 (G1) is based on simple SONOS architecture and capable to scale down to 40nm and supports auto grade temperature and quality. G1 is cost ...

The MXL-LVDS-DPHY-CSI2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY ...

The DesignWare Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accelerator, ...