Configurable AMBA bus SoC platform IP Core
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common ...
Source: design-reuse.com
📰 P Core News
Page 164 - P Core News Today
Fast, Ad-Free News Updates
Stay updated with breaking news from P Core. Real-time updates on events, politics, business and more.
MIPI D-PHY CSI-2 TX+ in TSMC 28nm HPC+
The MXL-DPHY-CSI2-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, which ...
Source: design-reuse.com
MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI
The Renesas MIPI D-PHY Transmitter/Receiver is useful 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process.
Mipid Phy Csi 2 Dsi Samsung 28n Fd Soi Ipid Phy Transmitter Receiver For Dsi Csi 2 Samsung 28nm Fd Soi Ipid Phy Csi Dsi Samsung 28nm Fd Soi P Core Ilicon Ip Emiconductor Ip
Source: design-reuse.com
Controller, Modem, Software Stack and Profiles for Dual Mode Bluetooth v5.2 and v5.3
BlueWiz is Mindtree’s Dual Mode Bluetooth Semiconductor IP, which supports v5.2 Bluetooth specification. Mindtree has invested over 500 person-years ...
Bluewiz Is Mindtree Dual Mode Bluetooth Semiconductor Dual Mode Bluetooth Semiconductor Dual Mode Baseband Digital Modem Dual Mode Bluetooth Luetooth Dual Mode Controller
Source: design-reuse.com
MIPI D-PHY Transmitter - Designed for SMIC 130nm
The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY Designed for SMIC 130nm.
Source: design-reuse.com
DPA & Fault Injection Resistant AES-ECB Cryptographic Core
Rambus DPA & Fault Injection Resistant AES-ECB Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks when ...
Cipher Block Chaining Authenticated Encryption Galois Counter Rambus Dpa Amp Fault Injection Resistant Aes Ecb Cryptographic Core Rambus Dpa Amp Fault Injection Resistant Aes Ecb Cryptographic Core P Core
Source: design-reuse.com
LPDDR4 multiPHY in TSMC (16nm) IP Core
LPDDR4 multiPHY: Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps - Maximum data rate is process technology dependent - Compatible with JEDEC ...
Source: design-reuse.com
ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and ...
Flash Interface Working Group Ebook Readers Hamming Code Error Code Correction Interface Working Group Control Registers
Source: design-reuse.com
TSMC CLN28HPC 28nm DDR 4/3 PHY
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, ...
Source: design-reuse.com
eMMC 4.51 Device Controller IP Core
The eMMC 4.51 Memory controller is compliant with the latest MMC 4.51 specification released by JEDEC. The controller provides a peak bandwidth of 104MB/s and supports all of the security features offered by this standard. It also permits the Host to partition and manage card data.
Source: design-reuse.com