Page 162 - P Core News Today

The Digital Blocks DB-DMAC-MC-AHB Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The Direct Memory ...

The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort ...

The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The ...

The USB 2.0 Device Controller IP Core is an USB 2.0 compliant device core with optional PCI, Custom, or AHB master/slave interfaces.

The GPU_OVERLAY IP Core (Figure 1) is a highly versatile on-screen display processor that allows high-quality anti-aliased bitmap graphics and text to ...

The S3ADSIQ50M12BT22ULLB is an ultra low power 12-bit dual-channel High-Speed SAR ADC IP. This IP includes two ADC channels sampling up-to 50MS/s including ...

The DesignWare 200/400G and 800G Ethernet MAC and PCS IP solutions enable a host to transmit and receive data over Ethernet. The PCS IP is optimized for ...

Arasans eMMC 5.1 Memory controller is compliant with the latest eMMC 5.1 specification released by JEDEC. The controller provides a peak bandwidth of ...

The HIP 3300 Serial RapidIO IP solution is a complete high-performance core that incorporates a logical layer, a transport layer, and a physical layer ...

The MXL-PHY-DSI-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The ...