Page 161 - P Core News Today

An optional add-on for Arteris® FlexNoC® and Ncore™ interconnect IP that helps automate interconnect timing closure. PIANO provides more and better ...

The MXL-CPHY-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master supporting ...

The sixth generation of the widely licensed CEVA-XC architecture, the CEVA-XC5 is optimized for IoT communication applications, 802.11n, PLC, 802.15.4g, ...

Credo is the world leading SerDes Technology Company offers silicon proven SerDes IP from “1.25G to 112G” data rate. SerDes PMA is silicon proven ...

The CC-202IP Cell, can be cascaded to form a multistage RF amplifier/LNA/Filter. The CC-202IP cell, possessing a single cell gain of 30dB with a phase ...

NSCores TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the hot carrier effect to ...

The bi-directional AHB/AHB Bridge is used to interconnect high-speed and low-speed AMBA AHB buses. The bridge supports synchronous clocks with any frequency ...

The Western Digital SweRV Core™ EH2 is an RV32IMAC, 9-stage, dual-threaded, dual-issue, superscalar, mostly in-order pipeline with some out-of-order ...

Mobiveils PCI Transparent Switch is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking ...

The Synopsys DesignWare® DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) ...