Page 63 - P Core News Today

The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor. ...

The ODT-LDO-IC-250M-16 is a low dropout (LDO), linear regulator for integration in a SoC. The LDO uses advanced control techniques to achieve excellent ...

The Expedera OriginTM E1 NPU (Neural Processing Unit) is a series of Artificial Intelligence processing cores which are individually optimized for a class ...

The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm with fully-parallel and ...

TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compression ...

The Arasan’s VESA DSC v1.2 Encoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports ...

The CT25207, in combination with the CT25203, implements a complete OPEN Alliance TC14 10BASE-T1S PMD Interface. The IP’s tasks are: • perform the ...

CompuRAM™ provides In Memory Computing (IMC) that will enable solutions for computing at the Edge to be more power efficient. At present, sensor data ...

AES256-XTS IP Core (AES256XTSIP) implement the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which ...

Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates with ...