Page 62 - P Core News Today

I3C is a new a standard from the MIPI Alliance that unifies and extends the legacy interfaces of I2C and SPI and adds new powerful features to support ...

"The CetraC Switch IP core is the ideal solution to interconnect any TSN, Ethernet and ARINC 664 Part 7 (AFDX) equipment for safety critical application. ...

Chips&Media MAPI is a high-resolution Image Processing IP. It can scale up/down and color space conversion on a frame-by-frame basis with various input ...

The Synopsys Advanced I2C/SMBus Controller and Target Device IP extends capabilities beyond the I2C Interface to include advanced features for system ...

PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE specification ...

A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a complete subsystem dedicated to maximizing performance, ...

The Silicon Creations wide-range 250Mbps to 12.7Gbps 4-lane Deserializer and Serializer macro includes all high-speed analog functions for four lanes ...

The AT256X1U110MAE0AC is organized as a 256-bit by 1 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in UMC 110 nm 1.2V/3.3V ...

The Arasan DSI Transmit Controller IP is designed to provide MIPI DSI 1.3 compliant high speed serial connectivity for mobile host processors using 1 ...

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution ...