Page 60 - P Core News Today

The Synopsys ARC Software Test Library (STL) for ARC Processors is a hardware safety mechanism, as defined in the ISO 26262 standard, implemented in software; ...

Weebit ReRAM (Resistive Random Access Memory), is an innovative Non-Volatile Memory (NVM) technology that can be easily integrated into any CMOS IC. ReRAM ...

A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a complete subsystem dedicated to maximizing performance, ...

The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY ...

The Camera Link® IP Core is a high-speed LVDS transmitter / receiver pair that conforms to the standard Camera Link protocol originally developed by ...

The TPS3215MP OSU processor is an IP Core solution designed for Xilinx FPGAs. TPS3215MP processors accept 4x FE/GE and 4x E1 client signals, process and ...

The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has ...

The DVB-S2X LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design for ...

The MXL-CD-PHY-CSITX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

Arteris IP FlexNoC AI Package accelerates development of next-generation deep neural network (DNN) and machine learning systems. Automate and optimize ...