Page 59 - P Core News Today

The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1. ...

The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, ...

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution ...

The ALTUS28TR is a highly integrated, mmWave, agile transceiver offering a versatile combination of high performance, low power consumption and configurability ...

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL cards ...

The MXL-DPHY-CSI-TX+-T-40ULP is a high-frequency, low-power, low-cost, source synchronous physical Layer supporting the MIPI Alliance Specification for ...

The MXL-DPHY-CSI-2-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, which ...

The highly granular DTS offers a significant area reduction in comparison to some standard in-chip thermal sensor solutions and supports high accuracy ...

AndesCore™ D23 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5/V5e architecture for embedded applications with small gate count, and ...

The CT25209 Digital IP core implements the MACPHY SPI protocol defined by the “OPEN Alliance TC6 Serial 10BASE-T1x MACPHY Interface specifications”. ...