Page 90 - P Core News Today

The MXL-D-PHY-DSITX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

The synchronous I2C interface is a block that interconnects an APB bus. The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C ...

Chevin Technology’s TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. Chevin Technology’s ...

The AlphaCORE Long-Reach (LR) Multi-Standard-Serdes (MSS) IP is a high-performance, low-power, DSP-based PHY. It is a highly configurable IP that supports ...

The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and ...

D&R provides a directory of inside secure 800g multi channel macsec engine from rambus

This IP is mainly responsible for controlling the charging process of a Li-Ion battery and for providing a regulated voltage to the system. The charging ...

Engineered at intoPIX, TicoRAW is an innovative, lossless quality, low-power, low-memory and line-based image processing and compression technology created ...

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller ...

Veriests SPI Master Controller IP provides an industry standard data communication channel between the AMBA APB and SPI buses. It supports SPI master ...