Page 92 - P Core News Today

"The CetraC EndSystem IP coreis the ideal solution to link your Avionic Computer System to a safe & secure embedded network as ARINC664p7, TSN or Safe ...

Synopsys DesignWare® DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM ...

LPDDR4 multiPHY: Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps - Maximum data rate is process technology dependent - Compatible with JEDEC ...

The 32 Gbps Multi-protocol SerDes PHY is designed for high performance at very low power for medium reach applications.

This 13.56 MHz NFC IP in generic low-cost 0.18 μm CMOS targets compatibility with ISO/IEC 14443 Type A at 106 to 424 kbit/s (compatible with NFC-equipped ...

The Quad Serial Peripheral Interface (OSPI) core is a serial data link (SPI) master which controls an external serial FLASH device. Reading and writing ...

Logic Fruit Technologies has designed & implemented DISPLAY PORT Transmitter & Receiver IP Cores supporting multiple line rates up to 8.1Gbps. The IP ...

Tamba Networks offers a highly configurable, extremely low latency, low gate count, Ethernet MAC & PCS soft core. The core is IEEE compliant. The ...

Non-blocking NxN Crossbar with N inputs ports and N output ports can be used in networking switches such as PCI, Ethernet, InfiniBand, etc. It provides ...

Embedded Analytics supports non-intrusive monitoring and smart analytics of standard interconnects from the Arm ecosystem, including AXI, ACE, ACE-lite, ...