Page 96 - P Core News Today

The New Wave DV Fibre Channel Upper Layer Protocol (FC-ULP) core provides a complete FC-4 layer hardware IP solution for the Fibre Channel Avionics Environment ...

The Expedera TimbreAI T3 is an ultra-low-power Artificial Intelligence (AI) Inference engine designed for audio noise reduction uses cases in power-constrained ...

1-VIA’s VSCOM4L400ALDO0V9 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulation across a wide range ...

The EIP-197 is a family of high speed Cryptographic Accelerators with embedded Classification Engine, Virtualization, Latency compensation to maintain ...

Rambus Compute Express Link (CXL) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, ...

CYB-RS-en core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number ...

MIL-STD-1553B IP Core implements MIL-STD1553B standard and provides single or multifunctional interface between host processor and MIL-STD-1553 bus ...

Rambus PCIe Controller IP for USB4 with AXI is a configurable and scalable PCIe controller Soft IP designed for implementations in USB4 devices. It supports ...

Dolphin Design provides a complete Power Management IPs platform towards three objectives To standardize and ease Power Regulation Network integration ...

The Synopsys DesignWare® HDMI 2.1 TX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, ...