Siemens Adds AI and Big-Data Management to Its Questa Verification EDA tools
It’s no secret that ASIC and ASSP designs are getting more complex. First, there’s that whole thing about Moore’s Law allowing design teams to put more transistors, gates, memory cells, transceivers, processors, and acceleration engines on a chip. And, if that weren’t enough, there’s the relatively new quest to stuff an increasing number of chiplets…
Wally Rhine Siemen Questa Wilson Research Group Mentor Graphics Verification Study Functional Verification Study
Source: eejournal.com