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Cadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to...

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Highlights: Cadence optimized its AI-driven RTL-to-GDS digital flow and delivered corresponding 5nm and 3nm RAKs for the Arm Neoverse V2 platform, enabling designers to get to market...

Highlights: Delivers up to 5X faster RTL convergence and up to 25% improved QoR RTL designers can rapidly get accurate insight into physical effects and actionable guidance on improving RTL Integrates with Cadence Cerebrus, and Cadence JedAI Platform for AI-driven RTL optimization

Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results

Highlights: • Certified Cadence flows are production-ready, and design IP is readily available for customers looking to create Intel 16 designs now • Customers can confidently deliver a wide variety of HPC, consumer and USMAG applications based on the Cadence-certified flows SAN JOSE, Calif., July 12, 2023 — Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced…

Highlights: Certified Cadence flows are production-ready, and design IP is readily available for customers looking to create Intel 16 designs now Customers can confidently deliver a wide variety of HPC, consumer and USMAG applications based on the Cadence-certified flows

Cadence today announced it has continued to expand its collaboration with Arm to advance mobile device silicon success, providing customers with a faster path to tapeout through use of Cadence® digital and verification tools and the new Arm® Total Compute Solutions 2023 (TCS23), which includes the Arm Cortex®-X4, Arm Cortex-A720 and Cortex-A520 CPUs and Immortalis™-G720, Mali™-G720 and Mali-G620 GPUs.

Highlights: • Companies collaborate to accelerate next-generation mobile, AI and hyperscale design innovation • Customers actively designing with new N3E and N4P PDKs • Cadence digital and custom/analog flows optimized to support N3E and N4P requirements, enabling optimal PPA results and improved designer productivity SAN JOSE, Calif., June 13, 2022—Cadence Design Systems, Inc. (Nasdaq: CDNS)…

Highlights: • MediaTek shrinks die area by 5% and reduces power by more than 6% with the Cadence Cerebrus floorplan optimization feature • Cadence collaborates with Renesas to deploy Cadence Cerebrus on two designs; achieves better performance on an advanced-node CPU design and a leakage power reduction on an MCU design SAN JOSE, Calif., June…