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Xeretec, Xerox, XMPie, and Vivid Laminating Technologies are coming together once more to host an event later this month that aims to showcase the latest innovations in short-run digital print and packaging.

Vivid Laminating Technologies has launched a new automatic tape applicator to increase automation and efficiency for users of its Veloblade Volta+ digital die-cutting systems.

Brighton-based One Digital had always outsourced die-cutting jobs. It had a sizeable array of equipment in its factory that allowed it to take on all manner of digital and litho work, including a vinyl Summa machine, so it was used to setting up dies and cutting guides, but die-cutting was something it had never really considered bringing in-house.

The SM3 hash algorithm is a cryptographic hash function designed by the Chinese Commercial Cryptography Administration Office (CCCAO) in order to propose ...

Tunable DES - Triple DES (ECB, CBC, CTR) accelerator - optional SCA protection The Data Encryption Standard (DES) is defined in FIPS PUB 46-3 as a symmetric-key algorithm. The triple DES (TDES) is block cipher that applies the DES algorithm three times to each data block. The TDES is defined in ANS X9.52-1998, NIST SP 800-67 rev-1 and ISO/IEC 18033-3:2010. TDES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting. View see the entire get in con...

Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network Our IP Core is the ideal solution to link all your equipment, sensor or actuator whatever the used protocol to an Avionic network in a safe & secure manner. It brings a high performance, low latency, safe and cyber-secure link between your equipment and the Avionic network based on ARINC664p7/Ethernet network. On the Avionic network side, CetraC technology is fully compliant with ARINC664 Part 7 and Ethern...

Device Secure Debug The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary Scan Architecture. Giving a full access to the internal system components of the device, the TAP interface can be a backdoor for hackers. Secure-IC offers a set of tools to secure the access to the device. This solution can be deployed in the Securyzr iSE or as a standalone IP. View see the entire

Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and programmable to support “any rate on any channel” (400G/200G/100G/50G/25G/10G/1G). It uses a novel time-sliced architecture that affords maximum density for high port count applications while maintaining industry-leading latencies...

MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is available on both TSMC’s industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process technologies. TSMC 22nm ultra-low power (22ULP) is an ideal foundry technology for applications including image processing, digital TVs, set-top boxes, ...

Galois Field based Reed Solomon Codec Reed Solomon FEC Error Correcting Code Based on Galois Field Arithmetic If RS is configured for 16 bits of error correction, then the same decoder/encoder can be used for any number of bit corrections from 1 to 15 This way the overhead can be reduced if desired. View see the entire get in contact with Reed Solomon FEC Error Correction IP