MIPI M-PHY Gear4 IP (Silicon Proven in UMC 28HPC+) The MIPI M-PHY Gear 4 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. The MIPI M-PHY provides robust testability by low cost Build-In-Self-Test (BIST), and receiver eye data monitoring and debugging function for embedded system.
Comcores 10G/25G Ethernet MAC provides a complete IEEE 802.3 Ethernet Layer 2 solution. The MAC IP core performs the Link function of the 10G/25G Ethernet .
MIPI D-PHY 4 Lane CSI2-TX 1.2G in TowerJazz 110nm The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control. View see the entire get in contact with
Block Diagram of the MIPI D-PHY 4 Lane CSI2-TX 1.2G in TowerJazz 110nm
Video Demo of the MIPI D-PHY 4 Lane CSI2-TX 1.2G in TowerJazz 110nm
AES (ECB-CBC-CFB-CTR), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumption compared to running the same algorithms in software.
The Crypto Accelerator Hardware Cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution, offering various levels of cryptographic acceleration performance.
They are easy to integrate into various SoC and FPGA architectures and development flows, and are all designed to maximize performance versus silicon area requirements. The Rambus IP core pass all NIST CAVP vectors. Several of the cores are also available in Differential Power Analysis (DPA) protected versions, extensively validated using the standardized Test Vector Leakage Assessment (TVLA) methodology. These Crypto accelerator core
Audio I2S-TDM Transceiver The IObundle I 2 S/TDM Transceiver core is a configurable audio interface core with transmission and receiving capabilities. It supports master/slave, internal DMA, multi-channel and several sample sizes and frame formats. The IP is currently supported for use in ASICs and FPGAs. View see the entire