Page 9 - Zip Core News Today

RBG DPA resistant cryptographic accelerator core Rambus DPA Resistant Cryptographic Accelerator Core RBG (NRBG+DRBG) prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. RBG DPA resistant cryptographic accelerator core. The DPA Resistant Hardware cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions across a wide array ...

GDDR6 Controller Northwest Logic GDDR6 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by GDDR6 SGRAM devices. The core also performs all initialization, refresh and power-down functions. The core uses bank management techniques to monitor the status of each GDDR6 SGRAM bank (up to 16 ...

The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, FPGA or ASSP technologies. ...

Dual-CORE HEVC/H.265 & AVC/H.264 combined codec for 8Kp60 WAVE541C is a dual-CORE codec IP, optimally architected for real-time encoding or decoding video at 8K60 in HEVC/H.265 and AVC/H.264 video formats. This IP core provides high-performance encoding and decoding capability up to 4K@120fps, 8K60fps with a dual-core architecture and an optimized silicon area for 4K Ultra-HD application. SoCs powered with WAVE541C will bring 8K content readiness to video generating devices such as a...

High Speed SPI AHB IP Core- Serial Peripheral Interface The Arasan High-Speed SPI - AHB IP Core provides a high-speed data communication channel between the AHB and SPI buses. The SPI - AHB bridge enables an AHB host to access a serial device at high speed through the SPI interface. The controller can be used in applications such as flash memory card and digital camera. The Arasan High Speed SPI – AHB IP Core is an RTL design in Verilog that implements an SPI – AHB controller on an A...