A formal-based approach for efficient RISC-V processor verif

In this article, we go through a formal-based, easy-to-deploy RISC-V processor verification application. We show how, together with a RISC-V ISA golden model and RISC-V compliance automatically generated checks, we can efficiently target bugs that would be out of reach for simulation.

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Laurent Arditi , Paul Sargent , Program Counter , Thomas Aird , Codasip Studio , Set Architecture , Coupled Memory , Point Unit , Verification App , Instruction Set Architecture , Design Under Test , Assertion Based Verification , A , Ormal Based , Approach , Or , Efficient , Risc V , Rocessor , Verification ,