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A formal-based approach for efficient RISC-V processor verification

In this article, we go through a formal-based, easy-to-deploy RISC-V processor verification application. We show how, together with a RISC-V ISA golden model and RISC-V compliance automatically generated checks, we can efficiently target bugs that would be out of reach for simulation. ....

Laurent Arditi , Paul Sargent , Program Counter , Thomas Aird , Codasip Studio , Set Architecture , Coupled Memory , Point Unit , Verification App , Instruction Set Architecture , Design Under Test , Assertion Based Verification , Ormal Based , Risc V ,

GigaDevice Semiconductor Inc.: GigaDevice to Showcase Comprehensive Industry Solutions at Embedded World 2023

NUREMBERG, Germany, March 13, 2023, a semiconductor industry leader in flash memory, 32-bit Microcontrollers (MCUs) and sensor technology, today announced that it will demonstrate its comprehensive solutions ....

Dennis Riedl , Exhibition Center Nuremberg , Gigadevice Semiconductor Inc , Embedded World , Microsoft Azure , Coupled Memory , Thin Film Transistor , Device Booth Hall , Device Flash Journey , Flashes Low Voltage , Device Media Relations ,