Imperas extends RISC-V processor verification ecosystem Imperas Software, a specialist in RISC-V processor verification technology, has announced the latest addition to its suite of RISC-V Verification IP (VIP) solutions. This solution includes Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D). The tests are designed to extend the company's current range of tests for ratified and near-ratified specifications tests, and complement the de facto industry adoption of the Imperas RISC-V verification reference model. Processor verification is the essential focus of any development team. Design bugs that are caught early help projects complete on schedule. The impact of late-stage bugs, and associated costs, can be significant.