Improves Productivity, Eliminates Tedious, Error-Prone Manual Effort SAN JOSE, CALIF. –– May 4, 2021 –– SmartDV™ Technologies, the leader in Design and Verification Intellectual Property (IP), today unveiled a tool suite that automates the protocol debugging process and testbench creation by eliminating tedious and error-prone manual approaches and improving productivity. The automation suite includes SmartViP Debug™, a tool that automatically identifies protocol violations with visual and tabular views, and SmartTestBench™. SmartTestBench automates the creation of testbench files, either through a graphical user interface or through text files, and supports a wide variety of verification scenarios. “Detecting, debugging and fixing protocol violations is a critical part of the verification flow,” says Deepak Kumar Tala, SmartDV’s managing director. “It is also time-consuming and typically requires detailed knowledge about the specific protocol being debugged. Developing testbenches manually is tedious work and often leads to errors. That’s why customers will find SmartDV’s automation tool suite a welcome addition to our product portfolio.”