TSS GDDR6 PHY on TSMC 12nm from Openedges The GDDR6 OPHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without the need to interrupt data traffic. The programmable timing PHY boundary combines flexibility with analog precision, and the result is ultra low PHY read/write latency between OMC and the GDDR6 DRAM without sacrificing performance. At the system level, the GDDR6 OPHY was designed with minimal package substrate layer and PCB layer count in mind. This enables the integration of a GDDR6 memory sub-system solution in cost sensitive applications, such as consumer edge devices, AI, GPU, HPC, STB, SSD controllers, and application processors.