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Processor architecture optimization is not a barrier for university researchers

With closed processor Instruction Set Architectures (ISA) with limited access to processor Intellectual Property (Arm and x86), university professors . ....

Instruction Set Architectures , Intellectual Property , Processor Security , Functional Safety , Intelligent Memories , Codasip University Program , Processor Architecture Optimization Is Nota Barrier For University Researchers , Codasip Blog , Keith Graham ,

Building a Swiss cheese model approach for processor verification

Processors all have high quality requirements and their reliability is the main concern of processor verification teams. Providing best-in-class quality . ....

Buildinga Swiss Cheese Model Approach For Processor Verification , Codasip Blog , Philippe Luc ,

Codasip appoints Japan EDA veteran

Codasip the leading supplier of customizable processor IP, today announced that EDA industry veteran Takaaki Akashi will head up its newly established presence in Japan. Akashi has over 25 years of solid experience in design industry, having held senior customer-facing roles at Synopsys and Cadence. ....

United Kingdom , Takaaki Akashi , Brett Cline , Riscv International , Chief Revenue Officer , Japanese Government , Artificial Intelligence ,

Measuring the complexity of processor bugs to improve testbench quality

I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and . ....

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality , Codasip Blog , Philippe Luc ,

Improve Your Verification Methodology: Hunt Bugs Flying in Squadrons

Creating a quality RISC-V processor requires a verification methodology that enforces the highest standards. In this article, Philippe Luc, Director of . ....

Philippe Luc , Improve Your Verification Methodology Hunt Bugs Flying In Squadrons , Codasip Blog , Philippe Luc ,