Synopsys Announces Euclide to Accelerate Design and Verification Productivity
Synopsys Announces Euclide to Accelerate Design and Verification Productivity Finds Bugs Early and Optimizes Code for Design Compiler, VCS and ZeBu News provided by Share this article Highlights: Correct-by-construction coding ensures RTL compatibility for Design Compiler and ZeBu Real-time checks help to avoid costly testbench errors and increase VCS performance Integration with Verdi for seamless debug and code development Built-in SystemVerilog/UVM compliance assures best coding practices across verification teams Synopsys, Inc. (Nasdaq: SNPS) today introduced Synopsys Euclide, the i...
Source: prnewswire.com