Voltage Optimization Modules IP Core
Voltage Optimization Modules Two patented IPs and a design methodology to estimate and track the minimum supply voltage (Vmin) for each individual circuit in the field: * TMFLT-S IP (Timing Fault Sensor) Estimates the Fmax/Vmin of the circuit during a calibration phase * TMFLT-R IP (Timing Fault Ring) : Tracks either the minimum voltage operation (Vmin) or the maximum clock frequency (Fmax) during run-time phase * TMFLT Sensor implementation methodology: Allows choosing the best register candidates to insert TMFLT Sensors. Allowing to minimize the area overhead to les...
Source: design-reuse.com