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Things have evolved beyond all expectation since I designed my first ASIC.

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

As semiconductor manufacturing technology advances, systems-on-chip (SoCs) have increased our capacity to contain more transistors in a smaller area, enabling greater computational power and functionality. The way of connecting components in an SoC needed to evolve to support the growing data communication demands.

Utilizing physically aware interconnect IP from trusted third-party vendors can reduce design time and increase productivity.

Today’s system-on-chip (SoC) devices may be composed of hundreds of functional blocks known as intellectual property (IP) blocks. Each of these IPs can contain hundreds of millions of transistors. Standard IPs like processors, memory, codecs and communication functions are usually acquired from third-party vendors.